Time Table


10:00



10:40
  Greetings from Chairman, the executive committee of Design Solution Forum 2014
   
  Michihiro Okada
Chairman, the executive committee of Design Solution Forum 2014
KYOCERA Document Solutions
   
  Keynote
   
 

The Trend of IoT & Next Generation Mobile Communications 5G and the Vision of Electronics


Toshiyuki Futakata
NTT DOCOMO

speaker
 
 

10:50

11:30

The pursuit of consistency on MFP SoC Development with SysML


Mamoru Kani
KYOCERA Document Solutions

The way to the software driven verification


Harunobu Miyashita
Fuji Xerox

The FPGA prototyping with V7 TAI Logic Module


Shuntaro Seno
Hitachi

The merged software development and SoC verification like this!


Tatsuro Miyakawa
FUJITSU SEMICONDUCTOR

The SystemVerilog Hackathon


<Moderator>
Harunobu Miyashita
DSForum Committee Member
Fuji Xerox

11:40

12:00

Solve issues by seeing differences between ASIC and FPGA design flow
- CME provides best design frlow -


Seiichi Futami
CM Engineering

The introduction of Atrenta's new solution, BugScope and SpyGlass FPGA-Kit


Nobutaka Ogiya
Atrenta

The high-performance scalable FPGA-based prototyping solution


Tomoyuki Tsuji
S2C Japan

The development of low-power object recognition processor on ASIP



Masaaki Ideno
Nihon Synopsys

12:10

12:50

「The HLS Talk」
The HLS recommendation by major tool vendors



<Moderator>
Takashi Kawabe
DSForum Committee Member
Konica Minolta

The pincer drive from upstream and downstream
Example of reducing development time on the large FPGA with verification



Yoshimasa Ishino
Mitsubishi Electric Micro-Computer Application Software

The introduction of debug method with an actual case



Kunihiko Tsuji
Kyoto Microcomputer

The virtual environment building with QEMU



Hiroyuki Tomiyama
Ritsumeikan Univ.

13:00

13:20

The effect and applicable domain of virtual prototyping



Kentaro Yasuda
Nihon Synopsys

The approach to performance verification



Tsuyoshi Yamaguchi
Verification Technology

HyperX - the next generation parallel processor



Takashi Hirano
Coherent Logix

The improvement by required life-cycle management for safety-critical FPGA and ASIC design



Takeshi Miyajima
Aldec Japan

13:30

13:50

The overview and success stories of HLS / verification system CyberWorkBench for ANSI-C and SystemC



Kazutoshi Wakabayashi
NEC

The 100% cycle accurate mode-based ESL tool "Carbon SoC Designer+" and cloud-based model creation site"Carbon IP Exchange"



Toshihisa Oishi
Carbon Design Systems Japan

The introduction of Xilinx All Programmable Abstraction



Kazunori Toyama
Xilinx

The unified flow building with consistency between RTL and UPF/SDC/IPXACT models



Rikuichi Kishimoto
DEFACTO Technologies

14:00

14:40

The HLS for ultrafast transport system



Masao Nakano
FUJITSU KANSAI-CHUBU NET-TECH

Shingo Kuroda
FUJITSU Microelectronics Solutions

「The Verification Talk」
The verification business to activate Japanese industry
~The forecast by verification "Takumi" about the direction of the future verification business



<Moderator>
Hirohisa Kotegawa
DSForum Committee Member
FUJITSU SEMICONDUCTOR

NoiseWiper, IP verification with Zynq



Kazuhiro Hiramoto
Morpho

Open source and HLS processing, Synthesijer
- in an effort to easy FPGA development with Java -



Takefumi Miyoshi
Wasa-Labo

14:50

15:10

The analysis of power and thermal on early stage of design and early development of power / thermal aware software by DOCEA POWER



Tsunemori Kawahara
Nextream

The comprehensive formal verification: the integration of the latest formal tool, VC Formal and Certitude from Synopsys



Yukio Mogi
Nihon Synopsys

The latest Altera Arria 10 SoC with ARM processors and development method for software designer



Takayuki Oyama
Altera Japan

The approach to design high performance SoC effectively in short period



Kazuyoshi Okazaki
Imagination Technologies

15:20

16:00

The challenges on MATLAB/Simulink model implementation to hardware and software



Mutsumi Saito
FUJITSU KYUSHU NETWORK TECHNOLOGIES

The eexamples of UVM verification environment building with IP-XACT



Ken-ichi Ozawa
Ricoh

「The Software-Test Talk」
The test-aware HW/SW design



<Moderator>
Tsuji Kunihiko
DSForum Committee Member
Kyoto Microcomputer

The improving the field power! The challenges and engineer cultivating on large development era



Takashi Kawabe
Konica Minolta

16:10

16:30

The layout design examples and methods on the advanced system LSI



Seiichiro Horiike
Alchip Technologies

The latest IP-XACT application examples: Introduction of auto-building of verification environment and full-synchronization of specification and design



Tsunemori Kawahara
Nextream

The debug method and features for FPGA-based prototyping



Fujio Otsuka
Nihon Synopsys

The computer-vision specific DSP and its development environment



Masayuki Shirahama
Nihon CEVA

16:40

17:20

The system verification examples on EXPEED development



Ryo Takami / Norihisa Matsumoto
Nikon

How to improve verification quality for 1 chip

- The application examples of formal functional verification -



Toshiya Uenishi
Renesas System Design

The software designer- driven hardware design examples



Naoya Morita
Ricoh

「The IP Talk」
What's user-friendly IP?



<Moderator>
Sadahiro Kimura
DSForum Committee Vice Chairman
Ricoh

 
17:40

19:30
  Reception Party
   
  * The networking event is limited to invited guests. The invitation card is required to attend.