9:20

9:30
Greetings from Chairman, the executive committee of Design Solution Forum 2017     3F "Chester House"

Sadahiro Kimura
Ricoh Company, Ltd.
9:30

10:30
Keynote     3F "Chester House"

「In the era of IoT/AI, how R&D would be changed and what would be required of engineers」

Tsuguo Nobe
Director and Chief Advanced Service Architect Business Development
Government and Policy Group
Intel K.K.

[/su_column]
 
Track A 4F "Blue Plum" Track B 3F "Henry House" Track C 3F "Chester House" Track D 4F "Hilltop" SP1 4F "Centuries" SP2 4F "Olive" SP3 2F "Queen's Hall"
10:40

11:20
A-1
「SystemC works for us, doesn't it?」

Yoshitaka Tateyama
KYOCERA Document Solutions Inc.

B-1
「RISC-V Technologies and Commercial Scenarios」

Shumpei Kawasaki
Software Hardware & Consulting LLC

C-1
「Acceleration of Deep Learning Inference on Raspberry Pi」

Koichi Nakamura
Idein Inc.

D-1
「Your cloud business with Unity」

Makoto Ito
Unity Technologies Japan G.K.

SP1-1
Software planning
SP2-1
Formal verification discussion

* registration was closed
11:30

11:50
A-2
「Virtual Prototyping Solution: Model Creation, Prototype Development, Software Debug on Prototype」

Takashi Ikeda
Nihon Synopsys G.K.

B-2
「RISC-V Based Application Specific Instruction-Set Processor Development」

Masaaki Ideno
Nihon Synopsys G.K.

C-2
「Introduction of worldwide No.1 VIP portfolio and synthesizable VIP (SimXL) which achieves faster verification」

Naoya Morita
Nextream Corporation
SmartDV

D-2
「We started functional safety services for LSI.」

Toshiyuki Hamatani
Verification Technology, Inc.

SP3-2
Biblio Battle

11:30-12:40
12:00

12:40
A-3
「Innovation to PoC Oriented system development」

Junichi Niitsuma
Socionext.Inc

B-3
「Introduction of Open-source processor architecture “RISC-V”」

msyksphinz (Handle Name)

* registration was closed
Lunch Time Lunch Time
12:50

13:30
Lunch Time Lunch Time
C-4
「Introduction of Cocytus, Deep Learning Framework for embedded systems」

Minoru Natsutani
Pasona Tech, Inc.

D-4
「Applications and future perspective of image sharpening technologies with deconvolution」

Jun Nishigata
CasleyConsulting, Inc.

SP3-1
Free Talk session: Questions to senior engineers

12:40-13:30

Interviewer
Takashi Kawabe
Konica Minolta, Inc.

Interviewee
Harunobu Miyashita
Fuji Xerox co., Ltd.

Kunihiko Tsuji
Kyoto Microcomputer Co., Ltd.
13:40

14:00
A-5
「Introduction of IDPA which allows to model and analyze power of system that has complecated execution modes」

Tsunemori Kawahara
Nextream Corporation
Intel/Docea

B-5
「Using Formal to Verify Safety-Critical Hardware for ISO 26262」

OneSpin Solutions Japan K.K

C-5
「Versatile deep learning vision platform for mobile, surveillance and automotive」

SEIICHI HORIE
CEVA

D-5
「Designing Computor Vision System by using reVISION Stack」

Louie Valeña
Xilinx Inc

14:10

14:50
A-6
「Renesas’ Efforts to Extend Application Range of Formal Verification」

Fumitaka Fukuzawa
Kota Sakai Renesas Electronics

B-6
「An Out-of-Order RISC-V processor written in Verilog HDL」

Masashi FUJINAMI

C-6
「GUINNESS: A GUI based binarized deep Neural Network Synthesizer for an FPGA implementation including a training」

Hiroki Nakahara
Tokyo Institute of Technology

* registration was closed
D-6
「User Experience as a Design Requirement for Engineers」

Masaaki Kurosu
The Open University of Japan

SP1-2
HW-SW Discussion * registration was closed
SP2-2
Special session:[Workshop] Design Computor Vision System with reVISION Stack

Naohiro Jinbo
Xilinx Inc

14:00~16:30

* registration was closed
15:00

15:20
A-7
「Introduction of New VC Formal Technologies」

Makoto Sugie
Nihon Synopsys G.K.

B-7
「Effective Virtual Prototype model based on SystemC」

Kiyoshi Makino
Mentor Graphics Japan Co.,Ltd.

C-7
「Low Power Consumption CNN-based Inference Engine for Embedded Vision Application」

Masaaki Ideno
Nihon Synopsys G.K.

D-7
「New generation FPGA board for HFT and HPC」

Takeshi Miyajima
Aldec Japan K.K.

15:30

16:10
A-8
「Case of utilization of the first RTL verification service using an offshore type Indian company in an image sensor developing venture company based on analog engineers」

Tomoyuki Akahori
Brookman Technology, Inc.

B-8
「System Synthesis and Verification of RISC-V based SoC Model Using the C2RTL Framework」

Tsuyoshi Isshiki
New System Vision Research and Development Institute / Tokyo Institute of Technology

C-8
「Deep Learning Acceleration by Algorithm/Hardware Co-design」

Shinya Takamaeda
Hokkaido University

D-8
「10nm Processor Trand 2017」

Hiroharu Shimizu
Techanalye Co.,Ltd

16:20

16:40
A-9
「Protium S1 FPGA-Based Prototyping Platform for Early Software Development」

Satoru Natsui
Cadence Design Systems, Japan

B-9
「RISC-V: Why does it matter?」

Roddy Urquhart
Codasip Ltd.

C-9
「TBD」

Tatsuya Noguchi
NIPPON SYSTEMWARE CO.,LTD.

D-9
「Introduction of integrated parallelized software development tool “SLX” which can generate parallelized software automatically for heterogeneous multicore system. 」

Tsunemori Kawahara
Nextream Corporation
Silexica

16:50

17:30
A-10
「Virtual platform for development of factory automation products」

Yasuhiro Ohashi
Mitsubishi Electric Corporation

B-10
「Implementing RISC-V with Polyphony:a Python-Based High-Level Synthesis Compiler」

Ryos Suzuki
Sinby Corporation

C-10
「AI Technology x Embedded Technology」

Masahiko Watanabe
CATS CO.,LTD.

D-10
「Proposal of a new design flow combining Silexica and high level synthesis」

Ryo Tosaka
RICOH COMPANY, LTD.